In a display device transmission system mounted on a mobile apparatus, with the increase of a transmission speed accompanying the increase in the number of grayscales and higher resolution of the display device, and with increasing complexity in the structure of the mobile apparatus, it is desired to reduce the number of wires in FPCs (Flexible Printed Circuits) passing through a hinge part of the mobile apparatus. Therefore, in recent years, a high speed serial transmission system has been in widespread use in the display device transmission system mounted on a mobile apparatus.
The display device transmission system, since mounted on a mobile apparatus, is required to be of low power consumption and to cope with various types of transmission lines having different characteristic impedances and resistance values, such as PWBs (Printed Wired Boards), FPCs, glass substrates, and so forth.
An example of a transmission system solving this type of problem, will be described below, with reference to the description of Patent Document 1.
FIG. 18 is a diagram (which is extracted from FIG. 6 of Patent Document 1) showing a configuration of a receiver circuit described in the abovementioned Patent Document 1, and FIG. 19 is a diagram (which is extracted from FIG. 1 of Patent Document 1) showing a configuration of a transmitter circuit described in the abovementioned Patent Document 1.
As shown in FIG. 19, a transmitter circuit 200, as described in the above-mentioned Patent Document 1, includes inverters 201 and 202, and first to third N-channel MOS transistors 203, 204, and 205.
The third N-channel MOS transistor 205 is turned ON, when signal transmission is performed and is turned OFF, when signal transmission is not performed. In this way, the amplitude voltage of a complementary signal output is reduced to decrease a delay time of a signal which is transmitted from the transmitter circuit 200 to the receiver circuit 100.
In the transmitter circuit 200, the first N-channel MOS transistor 203 and the second N-channel MOS transistor 204 are complementarily turned ON and OFF, based on a signal level of transmission data/DIN supplied to an input terminal 206. When the transmission data/DIN is LOW, the first N-channel MOS transistor 203 is turned ON, a first output terminal 208 has a ground potential, the second N-channel MOS transistor 204 is turned OFF, and a second output terminal 209 is in a high impedance state (referred to below as “floating potential”). When the transmission data/DIN is HIGH, the second N-channel MOS transistor 204 is turned ON, the second output terminal 209 has a ground potential, the first N-channel MOS transistor 203 is turned OFF, and the second output terminal 209 is in a high impedance state (“floating potential”).
A first input terminal 104 and a second input terminal 105 of the receiver circuit 100 in FIG. 18 are respectively connected to the first output terminal 208 and the second output terminal 209 of the transmitter circuit 200 of FIG. 19, via two transmission lines.
As shown in FIG. 18, the receiver circuit 100 includes an N-channel MOS transistor 101, an N-channel MOS transistor 102, a first receiver 110, a second receiver 120, a flip-flop circuit 130, and an inverter 103.
The first receiver 110 converts the difference between currents flowing through a first N-channel MOS transistor 113 and a second N-channel MOS transistor 114 to a voltage, and the second receiver 120 converts the difference between currents flowing through a third N-channel MOS transistor 123 and a fourth N-channel MOS transistor 124.
The flip-flop circuit 130 is an RS flip-flop formed of NANDs 131 and 132, each of which has an output cross-connected to an input of the other, and holds an output signal of the first receiver 110 and the second receiver 120. With regard to output of the flip-flop circuit 130, a value that is held is delivered from an output terminal 107 via the inverter 103.
Currents respectively flowing through the first N-channel MOS transistor 113 and the third N-channel MOS transistor 123 depend on a potential difference between a bias terminal 106 and the first input terminal 104, and currents respectively flowing through the second N-channel MOS transistor 114 and the fourth N-channel MOS transistor 124 depend on a potential difference between the bias terminal 106 and the second input terminal 105.
The potential of the first input terminal 104 depends on a resistance value of the N-channel MOS transistor 203, a resistance value of a transmission line, and a resistance value of the N-channel MOS transistor 101 of the receiver circuit 100, when the N-channel MOS transistor 203 of the transmitter circuit 200 is turned ON, and depends on a resistance value of the N-channel MOS transistor 101 of the receiver circuit 100, when the N-channel MOS transistor 203 of the transmitter circuit 200 is turned OFF.
In the same way, the potential of the second input terminal 105 depends on a combined resistance of an ON resistance value of the N-channel MOS transistor 204, a resistance value of a transmission line, and a resistance value of the N-channel MOS transistor 102 of the receiver circuit 100, when the N-channel MOS transistor 204 of the transmitter circuit 200 is turned ON, and depends on a resistance value of the N-channel MOS transistor 102 of the receiver circuit 100, when the N-channel MOS transistor 204 of the transmitter circuit 200 is turned OFF.
Therefore, since the current flowing from the receiver circuit 100 varies according to ON resistance value of the N-channel MOS transistors 203 and 204 in the transmitter circuit 200 and the resistance value of the transmission line, the differential current amplitude received by the receiver circuit 100 and power consumption of the receiver circuit 100 also vary.
As a method of solving the above problems, Patent Document 2 describes a transmission system. FIG. 20 is a diagram (extracted from FIG. 7 and the like, of Patent Document 2) showing a configuration of a receiver described in the abovementioned Patent Document 2, and FIG. 21 is a diagram (extracted from FIG. 3 of Patent Document 2) showing a configuration of a transmitter circuit described in the abovementioned Patent Document 2.
As shown in FIG. 20, the receiver apparatus described in the abovementioned Patent Document 2 includes a termination resistor 312 and a receiver circuit 330.
The receiver circuit 330 includes constant current sources 332 and 333 for supplying a constant current I0 to nodes 314 and 315 respectively, and a data detection circuit 334 for discriminating data transmitted, based on a voltage (that is, potential difference between the node 314 and the node 315) applied to the termination resistor 312.
The data detection circuit 334 is configured so as to supply currents I1 and I2 that are small to the extent of being negligible as comparison to the constant current I0, to the nodes 314 and 315, respectively.
In the transmission system described in the abovementioned Patent Document 2, with the constant current sources 332 and 333 provided in the receiver circuit 330, even if an ON resistance value of transistors 503 and 504 in a transmitter circuit 500 in FIG. 21 and a resistance value of a transmission line vary, a current flowing from the receiver circuit 330 is invariably kept constant, and power consumption of the receiver circuit 330 is invariably kept constant. Furthermore, with constant current sources 332 and 333 provided in the receiver circuit 330 and the termination resistor 312, the differential voltage amplitude between input terminals 308 and 309 is invariably kept constant.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2001-53598A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2006-14268A